//********************************
//******* zhoudaoxi **************
//********************************
module	AU8_ITPRE(
		reset,
		rx_clk155m,

		fp_to_ppfa,
		data_to_ppfa,
		
		fp_out,
		j1_out,
		spe_out,
		data_out,
		
		waddr_pl,
		wdata_pl,
		wen_pl,
		
		ptr_itpre_st1,
		ptr_itpre_st2,
		ptr_itpre_st3,
		ptr_itpre_st4,
		ptr_itpre_st5,
		ptr_itpre_st6,
		ptr_itpre_st7,
		ptr_itpre_st8,

		waddr_pl_h_t1,
		waddr_pl_h_t2,
		waddr_pl_h_t3,
		waddr_pl_h_t4,
		waddr_pl_h_t5,
		waddr_pl_h_t6,
		waddr_pl_h_t7,
		waddr_pl_h_t8,
		pi_chan_y3
		);

//*************************
input			reset;
input			rx_clk155m;

input			fp_to_ppfa;
input	[7:0]	data_to_ppfa;

output			fp_out;
output			j1_out;
output			spe_out;
output	[7:0]	data_out;

output	[9:0]	waddr_pl;
output	[8:0]	wdata_pl;
output			wen_pl;

output	[1:0]	ptr_itpre_st1;
output	[1:0]	ptr_itpre_st2;
output	[1:0]	ptr_itpre_st3;
output	[1:0]	ptr_itpre_st4;
output	[1:0]	ptr_itpre_st5;
output	[1:0]	ptr_itpre_st6;
output	[1:0]	ptr_itpre_st7;
output	[1:0]	ptr_itpre_st8;

output	[4:0]	waddr_pl_h_t1;
output	[4:0]	waddr_pl_h_t2;
output	[4:0]	waddr_pl_h_t3;
output	[4:0]	waddr_pl_h_t4;
output	[4:0]	waddr_pl_h_t5;
output	[4:0]	waddr_pl_h_t6;
output	[4:0]	waddr_pl_h_t7;
output	[4:0]	waddr_pl_h_t8;

output	[2:0]	pi_chan_y3;

//****************************
parameter PTR_MAX = 10'd782;
//parameter IDLE  = 3'b000;
parameter NORM	= 3'b001;
parameter LOP	= 3'b010;
parameter AIS	= 3'b011;
parameter INC	= 3'b100;
parameter DEC	= 3'b101;

//****************************
parameter		HP_NUM = 4'd8;

reg		[2:0]	hp_chan,hp_chan_y1,hp_chan_y2,hp_chan_y3,hp_chan_y4,hp_chan_y5,hp_chan_y6;
reg		[8:0]	cnt270_col;
reg		[3:0]	cnt9_row;

wire	[17:0]	h1h2_ptr_y2;
reg		[17:0]	h1h2_ptr_y3;
reg		[17:0]	h1h2_ptr_y3_temp;

wire	[9:0]	ptr_old;
wire	[15:0]	ptr_new;
reg		[1:0]	ptr_new_y1_tmp;
wire	[9:0]	ptr_new_y1;
wire	[4:0]	i_bit_inv;
wire	[4:0]	d_bit_inv;
wire	[2:0]	i_inv_amount;
wire	[2:0]	d_inv_amount;
wire			i_bit_invert_tmp;
wire			d_bit_invert_tmp;
wire			newp_flag_tmp;
wire			allone_flag_tmp;
wire			n_ovf_tmp;
wire			ptr_continue_tmp;
wire			ptr_is_exact_tmp;
wire			refresh_ind_tmp;
wire			inc_ptr_tmp;
wire			dec_ptr_tmp;

reg				newp_flag;
reg				allone_flag;
reg				norm_flag;
reg				n_ovf_ptr;
reg				ptr_continue;
reg				refresh_ind;
reg				ptr_is_exact;
reg				inc_ptr;
reg				dec_ptr;

wire	[9:0]	ptr_vlue_old_y1;
wire	[1:0]	allone_cnt_old_y1;
wire	[2:0]	newp_inv_cnt_old_y1;
wire	[1:0]	cntinu_cnt_old_y1;
wire	[2:0]	st_old_y1;

wire	[9:0]	ptr_vlue_old_y2;
wire	[1:0]	allone_cnt_old_y2;
wire	[2:0]	newp_inv_cnt_old_y2;
wire	[1:0]	cntinu_cnt_old_y2;
wire	[2:0]	st_old_y2;

reg		[9:0]	ptr_vlue_old_y3;
reg		[1:0]	allone_cnt_old_y3;
reg		[2:0]	newp_inv_cnt_old_y3,newp_inv_cnt_old_p;
reg		[1:0]	cntinu_cnt_old_y3;
reg		[2:0]	st_old_y3;

reg		[9:0]	ptr_n_vlue_old_y3;

reg		[9:0]	ptr_vlue_old_p;
reg		[9:0]	ptr_n_vlue_old_p;
reg		[1:0]	cntinu_cnt_old_p;
reg		[2:0]	st_old_p;		
		
reg		[1:0]	continue_cnt,continue_cnt_y1;
reg		[1:0]	allone_cnt_new,allone_cnt_new_y1;
reg		[2:0]	newp_inv_cnt_new,newp_inv_cnt_new_y1;
reg		[9:0]	ptr_vlue_new,ptr_vlue_new_y1;
reg		[2:0]	st_new,st_new_y1;

reg				allone_cnt_old_eq2;
reg				newp_inv_cnt_old_eq7;
reg		[1:0]	allone_cnt_old_add1;
reg		[2:0]	newp_inv_cnt_old_add1;

reg		[9:0]	ptr_vlue_old_add1;
reg		[9:0]	ptr_vlue_old_sub1;

reg		[7:0]	data_in,data_in_y1,data_in_y2,data_in_y3,data_in_y4;
reg				fp_to_ppfa_y1,fp_to_ppfa_y2,fp_to_ppfa_y3,fp_to_ppfa_y4;

reg		[1:0]	ptr_itpre_st1,ptr_itpre_st2,ptr_itpre_st3,ptr_itpre_st4;
reg		[1:0]	ptr_itpre_st5,ptr_itpre_st6,ptr_itpre_st7,ptr_itpre_st8;

//****************
reg				h1_pos,h1_pos_y1,h1_pos_y2,h1_pos_y3;
reg				h2_pos,h2_pos_y1,h2_pos_y2,h2_pos_y3,h2_pos_y4,h2_pos_y5;
reg				h31h32h33_pos,h31h32h33_pos_y1,h31h32h33_pos_y2;
reg				h33_nn1n2_pos,h33_nn1n2_pos_y1,h33_nn1n2_pos_y2;

reg				hp_spe,hp_spe_y1,hp_spe_y2;
reg				col0_en,col0_en_y1,col0_en_y2,col0_en_y3,col0_en_y4,col0_en_y5;
reg		[1:0]	cnt3_col,cnt3_col_y1,cnt3_col_y2,cnt3_col_y3,cnt3_col_y4,cnt3_col_y5;

reg				spe_tmp,spe_tmp_y1,spe_tmp_y2,spe_tmp_y3;
wire	[9:0]	j1_marker_old_y2;
wire	[9:0]	j1_marker_old_y3;
reg		[9:0]	j1_marker_old_y4;
reg		[9:0]	j1_marker;
reg				j1_marker_eq_MAX;

reg				fp_out;
reg				j1_out;
reg				spe_out;
reg		[7:0]	data_out;

wire	[2:0]	pi_chan_y3;

//********************************************
reg		[4:0]	waddr_pl_h_t1,waddr_pl_h_t2,waddr_pl_h_t3,waddr_pl_h_t4;
reg		[4:0]	waddr_pl_h_t5,waddr_pl_h_t6,waddr_pl_h_t7,waddr_pl_h_t8;
reg		[4:0]	waddr_pl_h;
wire	[8:0]	wdata_pl;
wire	[9:0]	waddr_pl;
wire			wen_pl;


//********************************************
//********************************************
assign pi_chan_y3 = hp_chan_y4;

always @(posedge rx_clk155m or posedge reset)
begin
 	if(reset == 1'b1)
		hp_chan <= 0;
	else if(fp_to_ppfa == 1'b1)
		hp_chan <= 1;
	else
		hp_chan <= hp_chan + 1;
end

always @(posedge rx_clk155m or posedge reset)
begin
 	if(reset == 1'b1)
		cnt270_col <= 0;
	else if(fp_to_ppfa == 1'b1)
		cnt270_col <= 0;
	else if(hp_chan == (HP_NUM-1))
		if(cnt270_col == 269)
			cnt270_col <= 0;
		else
			cnt270_col <= cnt270_col + 1;
end

always @(posedge rx_clk155m or posedge reset)
begin
 	if(reset == 1'b1)
		cnt9_row <= 0;
	else if(fp_to_ppfa == 1'b1)
		cnt9_row <= 0;
	else if((hp_chan == (HP_NUM-1))&&(cnt270_col == 269))
		if(cnt9_row == 8)
			cnt9_row <= 0;
		else
			cnt9_row <= cnt9_row + 1;
end

always @(posedge rx_clk155m or posedge reset)
begin
 	if(reset == 1'b1)
		cnt3_col <= 0;
	else if(fp_to_ppfa == 1'b1)
		cnt3_col <= 0;
	else if(hp_chan == (HP_NUM-1))
		if(cnt3_col == 2)
			cnt3_col <= 0;
		else
			cnt3_col <= cnt3_col + 1;
end

always @(posedge rx_clk155m or posedge reset)
begin
 	if(reset == 1'b1)
		h1_pos <= 0;
	else if((cnt9_row == 3)&&(cnt270_col == 0))
		h1_pos <= 1;
	else
		h1_pos <= 0;
end

always @(posedge rx_clk155m or posedge reset)
begin
 	if(reset == 1'b1)
		h2_pos <= 0;
	else if((cnt9_row==3)&&(cnt270_col==3))
		h2_pos <= 1;
	else
		h2_pos <= 0;
end

always @(posedge rx_clk155m or posedge reset)
begin
 	if(reset == 1'b1)
		h31h32h33_pos <= 0;
	else if((cnt9_row==3)&&(cnt270_col>=6)&&(cnt270_col<=8))
		h31h32h33_pos <= 1;
	else
		h31h32h33_pos <= 0;
end

always @(posedge rx_clk155m or posedge reset)
begin
 	if(reset == 1'b1)
		h33_nn1n2_pos <= 0;
	else if((cnt9_row==3)&&(cnt270_col>=9)&&(cnt270_col<=11))
		h33_nn1n2_pos <= 1;
	else
		h33_nn1n2_pos <= 0;
end

always @(posedge rx_clk155m or posedge reset)
begin
 	if(reset == 1'b1)
		hp_spe <= 0;
	else if((cnt9_row==3)&&(cnt270_col>=6))
		hp_spe <= 1;
	else if(cnt270_col>=9)
		hp_spe <= 1;
	else
		hp_spe <= 0;
end

always @(posedge rx_clk155m or posedge reset)
begin
 	if(reset == 1'b1)
		data_in <= 0;
	else
		data_in <= data_to_ppfa;
end

always @(posedge rx_clk155m or posedge reset)
begin
 	if(reset == 1'b1)
 		begin
 		hp_chan_y1 <= 0;
 		hp_chan_y2 <= 0;
 		hp_chan_y3 <= 0;
		hp_chan_y4 <= 0;
		hp_chan_y5 <= 0;
		hp_chan_y6 <= 0;
 		h1_pos_y1 <= 0;
 		h1_pos_y2 <= 0;
 		h1_pos_y3 <= 0;
		h2_pos_y1 <= 0;
		h2_pos_y2 <= 0;
		h2_pos_y3 <= 0;
		h2_pos_y4 <= 0;
		h2_pos_y5 <= 0;
		data_in_y1 <= 0;
		data_in_y2 <= 0;
		data_in_y3 <= 0;
		data_in_y4 <= 0;
		fp_to_ppfa_y1 <= 0;
		fp_to_ppfa_y2 <= 0;
		fp_to_ppfa_y3 <= 0;
		fp_to_ppfa_y4 <= 0;
		cnt3_col_y1 <= 0;
		cnt3_col_y2 <= 0;
		cnt3_col_y3 <= 0;
		cnt3_col_y4 <= 0;
		cnt3_col_y5 <= 0;
		end
	else
		begin
		hp_chan_y1 <= hp_chan;
 		hp_chan_y2 <= hp_chan_y1;
 		hp_chan_y3 <= hp_chan_y2;
		hp_chan_y4 <= hp_chan_y3;
		hp_chan_y5 <= hp_chan_y4;
		hp_chan_y6 <= hp_chan_y5;
		h1_pos_y1 <= h1_pos;
		h1_pos_y2 <= h1_pos_y1;
		h1_pos_y3 <= h1_pos_y2;
		h2_pos_y1 <= h2_pos;
		h2_pos_y2 <= h2_pos_y1;
		h2_pos_y3 <= h2_pos_y2;
		h2_pos_y4 <= h2_pos_y3;
		h2_pos_y5 <= h2_pos_y4;
		data_in_y1 <= data_in;
		data_in_y2 <= data_in_y1;
		data_in_y3 <= data_in_y2;
		data_in_y4 <= data_in_y3;
		fp_to_ppfa_y1 <= fp_to_ppfa;
		fp_to_ppfa_y2 <= fp_to_ppfa_y1;
		fp_to_ppfa_y3 <= fp_to_ppfa_y2;
		fp_to_ppfa_y4 <= fp_to_ppfa_y3;
		cnt3_col_y1 <= cnt3_col;
		cnt3_col_y2 <= cnt3_col_y1;
		cnt3_col_y3 <= cnt3_col_y2;
		cnt3_col_y4 <= cnt3_col_y3;
		cnt3_col_y5 <= cnt3_col_y4;
		end
end

//****************************
always @(h1_pos_y3 or h2_pos_y3 or data_in_y3 or h1h2_ptr_y3)
begin
	if(h1_pos_y3 == 1'b1)
		h1h2_ptr_y3_temp <= {data_in_y3,h1h2_ptr_y3[9:0]};
	else if(h2_pos_y3 == 1'b1)
		h1h2_ptr_y3_temp <= {h1h2_ptr_y3[17:10],h1h2_ptr_y3[11:10],data_in_y3};
	else
		h1h2_ptr_y3_temp <= 18'd0;
end

//always @(posedge rx_clk155m or posedge reset) begin
// 	if(reset == 1'b1)
//		h1h2_ptr_y3 <= 0;
//	else
//		h1h2_ptr_y3 <= h1h2_ptr_y2;
//end
always @(h1h2_ptr_y2) begin
		h1h2_ptr_y3 <= h1h2_ptr_y2;
end


//AU8_PTR_RAM64x18 U_B_PTR_RAM64x18(
//	.clock			(rx_clk155m),
//	.wraddress		({5'd0,hp_chan_y4}),
//	.data			(h1h2_ptr_y3_temp),
//	.wren			((h1_pos_y3|h2_pos_y3)),
	
//	.rdaddress		({5'd0,hp_chan_y2}),
//	.q				(h1h2_ptr_y2)
//	);

AU8_PTR_RAM64x18                   U_B_PTR_RAM64x18(
   .clka                           ( rx_clk155m ),
   .wea                            ( (h1_pos_y3|h2_pos_y3) ),
   .addra                          ( {5'd0,hp_chan_y4} ),
   .dina                           ( h1h2_ptr_y3_temp ),
   .clkb                           ( rx_clk155m ),
   .addrb                          ( {5'd0,hp_chan_y2} ),
   .doutb                          ( h1h2_ptr_y2 )
   );


assign ptr_old = h1h2_ptr_y3[9:0];
assign ptr_new = {h1h2_ptr_y3[17:10],data_in_y3};
assign ptr_new_y1 = {ptr_new_y1_tmp,data_in_y4};
assign i_bit_inv = {ptr_new[1]^ptr_old[1],ptr_new[3]^ptr_old[3],ptr_new[5]^ptr_old[5],ptr_new[7]^ptr_old[7],ptr_new[9]^ptr_old[9]};
assign d_bit_inv = {ptr_new[0]^ptr_old[0],ptr_new[2]^ptr_old[2],ptr_new[4]^ptr_old[4],ptr_new[6]^ptr_old[6],ptr_new[8]^ptr_old[8]};

assign i_inv_amount = i_bit_inv[0]+i_bit_inv[1]+i_bit_inv[2]+i_bit_inv[3]+i_bit_inv[4];
assign d_inv_amount = d_bit_inv[0]+d_bit_inv[1]+d_bit_inv[2]+d_bit_inv[3]+d_bit_inv[4];

assign i_bit_invert_tmp = (i_inv_amount > 2);
assign d_bit_invert_tmp = (d_inv_amount > 2);

assign allone_flag_tmp = (ptr_new == 16'hffff);
assign norm_flag_tmp = ((ptr_new[15:12]==4'b0110)||(ptr_new[15:12]==4'b1110)||(ptr_new[15:12]==4'b0010)||(ptr_new[15:12]==4'b0100)||(ptr_new[15:12]==4'b0111));
assign newp_flag_tmp = ((ptr_new[15:12]==4'b1001)||(ptr_new[15:12]==4'b0001)||(ptr_new[15:12]==4'b1101)||(ptr_new[15:12]==4'b1011)||(ptr_new[15:12]==4'b1000));
		
assign n_ovf_tmp = (ptr_new[9:0] <= PTR_MAX);
assign ptr_continue_tmp = (ptr_new[9:0] == ptr_old);
assign ptr_is_exact_tmp = (ptr_new[9:0] == ptr_n_vlue_old_y3);

assign refresh_ind_tmp = ((norm_flag_tmp==1'b1)&&(ptr_continue_tmp==1'b1)&&(cntinu_cnt_old_y3>=1)&&(n_ovf_tmp==1'b1));
assign inc_ptr_tmp	= ((i_bit_invert_tmp==1'b1)&&(d_bit_invert_tmp==1'b0)&&(cntinu_cnt_old_y3>=2));
assign dec_ptr_tmp	= ((i_bit_invert_tmp==1'b0)&&(d_bit_invert_tmp==1'b1)&&(cntinu_cnt_old_y3>=2));

always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		begin
		ptr_new_y1_tmp <= 0;
		newp_flag <= 0;
		allone_flag <= 0;
		norm_flag <= 0;
		n_ovf_ptr <= 0;
		ptr_continue <= 0;
		refresh_ind <= 0;
		ptr_is_exact <= 0;
		inc_ptr <= 0;
		dec_ptr <= 0;
		end
	else
		begin
		ptr_new_y1_tmp <= ptr_new[9:8];
		newp_flag <= newp_flag_tmp;
		allone_flag <= allone_flag_tmp;
		norm_flag <= norm_flag_tmp;
		n_ovf_ptr <= n_ovf_tmp;
		ptr_continue <= ptr_continue_tmp;
		refresh_ind <= refresh_ind_tmp;
		ptr_is_exact <= ptr_is_exact_tmp;
		inc_ptr <= inc_ptr_tmp;
		dec_ptr <= dec_ptr_tmp;
		end
end

always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		allone_cnt_old_eq2 <= 0;
	else if(allone_cnt_old_y3 == 2)
		allone_cnt_old_eq2 <= 1;
	else
		allone_cnt_old_eq2 <= 0;
end

always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		newp_inv_cnt_old_eq7 <= 0;
	else if(newp_inv_cnt_old_y3 == 7)
		newp_inv_cnt_old_eq7 <= 1;
	else
		newp_inv_cnt_old_eq7 <= 0;
end

always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		begin
		allone_cnt_old_add1 <= 0;
		newp_inv_cnt_old_add1 <= 0;
		end
	else
		begin
		allone_cnt_old_add1 <= allone_cnt_old_y3 + 1'b1;
		newp_inv_cnt_old_add1 <= newp_inv_cnt_old_y3 + 1'b1;
		end
end

always @(norm_flag or n_ovf_ptr or ptr_continue or cntinu_cnt_old_p)
begin
	if((norm_flag == 1'b1)&&(n_ovf_ptr == 1'b1)&&(ptr_continue == 1'b1))
		if(cntinu_cnt_old_p == 2'd3)
			continue_cnt <= 2'd3;
		else
			continue_cnt <= cntinu_cnt_old_p + 1;
	else
		continue_cnt <= 2'd0;
end

always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		ptr_vlue_old_add1 <= 0;
	else
		if(ptr_vlue_old_y2 == PTR_MAX)
			ptr_vlue_old_add1 <= 0;
		else
			ptr_vlue_old_add1 <= ptr_vlue_old_y2 + 1'b1;
end

always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		ptr_vlue_old_sub1 <= 0;
	else
		if(ptr_vlue_old_y2 == 0)
			ptr_vlue_old_sub1 <= PTR_MAX;
		else
			ptr_vlue_old_sub1 <= ptr_vlue_old_y2 - 1'b1;
end

always @(st_old_y3 or ptr_vlue_old_y3 or ptr_vlue_old_add1 or ptr_vlue_old_sub1)
begin
	case(st_old_y3)
		INC:ptr_n_vlue_old_y3 <= ptr_vlue_old_add1;
		DEC:ptr_n_vlue_old_y3 <= ptr_vlue_old_sub1;
		default:ptr_n_vlue_old_y3 <= ptr_vlue_old_y3;
	endcase
end

always @ (st_old_p or allone_flag or newp_flag or refresh_ind or n_ovf_ptr or ptr_is_exact or inc_ptr or dec_ptr
		or ptr_new_y1 or allone_cnt_old_eq2 or newp_inv_cnt_old_eq7 or ptr_vlue_old_p or ptr_n_vlue_old_p
		or allone_cnt_old_add1 or newp_inv_cnt_old_add1 or newp_inv_cnt_old_p)
begin
	case(st_old_p)
		INC:begin
			casex({allone_flag,newp_flag,ptr_is_exact})
			3'b1xx:begin
				if(allone_cnt_old_eq2)
					begin
					ptr_vlue_new <= 0;
					allone_cnt_new <= 0;
					newp_inv_cnt_new <= 0;
					st_new <= AIS;
					end
				else
					begin
					ptr_vlue_new <= ptr_vlue_old_p;
					allone_cnt_new <= allone_cnt_old_add1;
					newp_inv_cnt_new <= newp_inv_cnt_old_p;
					st_new <= NORM;
					end
				end
			3'b01x:begin
				casex({newp_inv_cnt_old_eq7,n_ovf_ptr})
				2'b1x:begin
					ptr_vlue_new <= 0;
					allone_cnt_new <= 0;
					newp_inv_cnt_new <= 0;
					st_new <= LOP;
					end
				2'b01:begin
					ptr_vlue_new <= ptr_new_y1;
					allone_cnt_new <= 0;
					newp_inv_cnt_new <= newp_inv_cnt_old_add1;
					st_new <= NORM;
					end
				2'b00:begin
					ptr_vlue_new <= ptr_vlue_old_p;
					allone_cnt_new <= 0;
					newp_inv_cnt_new <= newp_inv_cnt_old_add1;
					st_new <= NORM;
					end
				endcase
				end
			3'b001:begin
				ptr_vlue_new <= ptr_n_vlue_old_p;
				allone_cnt_new <= 0;
				newp_inv_cnt_new <= 0;
				st_new <= NORM;
				end
			3'b000:begin
				//ptr_vlue_new <= ptr_vlue_old_p;
				ptr_vlue_new <= ptr_n_vlue_old_p;
				allone_cnt_new <= 0;
				newp_inv_cnt_new <= 0;
				st_new <= NORM;
				end
			endcase
		end
			
		DEC:begin
			casex({allone_flag,newp_flag,ptr_is_exact})
			3'b1xx:begin
				if(allone_cnt_old_eq2)
					begin
					ptr_vlue_new <= 0;
					allone_cnt_new <= 0;
					newp_inv_cnt_new <= 0;
					st_new <= AIS;
					end
				else
					begin
					ptr_vlue_new <= ptr_vlue_old_p;
					allone_cnt_new <= allone_cnt_old_add1;
					newp_inv_cnt_new <= newp_inv_cnt_old_p;
					st_new <= NORM;
					end
				end
			3'b01x:begin
				casex({newp_inv_cnt_old_eq7,n_ovf_ptr})
				2'b1x:begin
					ptr_vlue_new <= 0;
					allone_cnt_new <= 0;
					newp_inv_cnt_new <= 0;
					st_new <= LOP;
					end
				2'b01:begin
					ptr_vlue_new <= ptr_new_y1;
					allone_cnt_new <= 0;
					newp_inv_cnt_new <= newp_inv_cnt_old_add1;
					st_new <= NORM;
					end
				2'b00:begin
					ptr_vlue_new <= ptr_vlue_old_p;
					allone_cnt_new <= 0;
					newp_inv_cnt_new <= newp_inv_cnt_old_add1;
					st_new <= NORM;
					end
				endcase
				end
			3'b001:begin
				ptr_vlue_new <= ptr_n_vlue_old_p;
				allone_cnt_new <= 0;
				newp_inv_cnt_new <= 0;
				st_new <= NORM;
				end
			3'b000:begin
				//ptr_vlue_new <= ptr_vlue_old_p;
				ptr_vlue_new <= ptr_n_vlue_old_p;
				allone_cnt_new <= 0;
				newp_inv_cnt_new <= 0;
				st_new <= NORM;
				end
			endcase
		end
		
		AIS:begin
			casex({allone_flag,newp_flag,refresh_ind})
			3'b1xx:begin
				ptr_vlue_new <= 0;
				newp_inv_cnt_new <= 0;
				st_new <= AIS;
				end
			3'b01x:begin
				casex({n_ovf_ptr,newp_inv_cnt_old_eq7})
				2'b1x:begin
					ptr_vlue_new <= ptr_new_y1;
					newp_inv_cnt_new <= 0;
					st_new <= NORM;
					end
				2'b01:begin
					ptr_vlue_new <= 0;
					newp_inv_cnt_new <= 0;
					st_new <= LOP;
					end
				2'b00:begin
					ptr_vlue_new <= 0;
					newp_inv_cnt_new <= newp_inv_cnt_old_add1;
					st_new <= AIS;
					end
				endcase
				end
			3'b001:begin
				ptr_vlue_new <= ptr_new_y1;
				newp_inv_cnt_new <= 0;
				st_new <= NORM;
				end
			default:begin
				if(newp_inv_cnt_old_eq7)
					begin
					ptr_vlue_new <= 0;
					newp_inv_cnt_new <= 0;
					st_new <= LOP;
					end
				else
					begin
					ptr_vlue_new <= 0;
					newp_inv_cnt_new <= newp_inv_cnt_old_add1;
					st_new <= AIS;
					end
				end
			endcase
			allone_cnt_new <= 0;
		end

		LOP:begin
			casex({allone_flag,refresh_ind,allone_cnt_old_eq2})
				3'b1x1:begin
					ptr_vlue_new <= 0;
					allone_cnt_new <= 0;
					st_new <= AIS;
					end
				3'b1x0:begin
					ptr_vlue_new <= 0;
					allone_cnt_new <= allone_cnt_old_add1;
					st_new <= LOP;
					end
				3'b01x:begin
					ptr_vlue_new <= ptr_new_y1;
					allone_cnt_new <= 0;
					st_new <= NORM;
					end
				default:begin
					ptr_vlue_new <= 0;
					allone_cnt_new <= 0;
					st_new <= LOP;
					end
			endcase
			newp_inv_cnt_new <= 0;
		end

		NORM:begin
			casex({allone_flag,newp_flag,refresh_ind,inc_ptr,dec_ptr})
			5'b1xxxx:begin
				if(allone_cnt_old_eq2)
					begin
					ptr_vlue_new <= 0;
					allone_cnt_new <= 0;
					newp_inv_cnt_new <= 0;
					st_new <= AIS;
					end
				else
					begin
					ptr_vlue_new <= ptr_vlue_old_p;
					allone_cnt_new <= allone_cnt_old_add1;
					newp_inv_cnt_new <= newp_inv_cnt_old_p;
					st_new <= NORM;
					end
				end
			5'b01xxx:begin
				casex({newp_inv_cnt_old_eq7,n_ovf_ptr})
					2'b1x:begin
						ptr_vlue_new <= 0;
						allone_cnt_new <= 0;
						newp_inv_cnt_new <= 0;
						st_new <= LOP;
						end
					2'b01:begin
						ptr_vlue_new <= ptr_new_y1;
						allone_cnt_new <= 0;
						newp_inv_cnt_new <= newp_inv_cnt_old_add1;
						st_new <= NORM;
						end
					2'b00:begin
						ptr_vlue_new <= ptr_vlue_old_p;
						allone_cnt_new <= 0;
						newp_inv_cnt_new <= newp_inv_cnt_old_add1;
						st_new <= NORM;
						end
				endcase
				end	
			5'b001xx:begin
				ptr_vlue_new <= ptr_new_y1;
				allone_cnt_new <= 0;
				newp_inv_cnt_new <= 0;
				st_new <= NORM;
				end
			5'b0001x:begin
				ptr_vlue_new <= ptr_vlue_old_p;
				allone_cnt_new <= 0;
				newp_inv_cnt_new <= 0;
				st_new <= INC;
				end
			5'b00001:begin
				ptr_vlue_new <= ptr_vlue_old_p;
				allone_cnt_new <= 0;
				newp_inv_cnt_new <= 0;
				st_new <= DEC;
				end
			default:begin
				if(newp_inv_cnt_old_eq7)
					begin
					ptr_vlue_new <= 0;
					allone_cnt_new <= 0;
					newp_inv_cnt_new <= 0;
					st_new <= LOP;
					end
				else
					begin
					ptr_vlue_new <= ptr_vlue_old_p;
					allone_cnt_new <= 0;
					newp_inv_cnt_new <= newp_inv_cnt_old_add1;
					st_new <= NORM;
					end
				end
			endcase
		end
		
		default:begin
			ptr_vlue_new <= 0;
			allone_cnt_new <= 0;
			newp_inv_cnt_new <= 0;
			st_new	<= AIS;
		end
	endcase
end

always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		begin
		//ptr_vlue_old_y2 <= 0;
		//allone_cnt_old_y2 <= 0;
		//newp_inv_cnt_old_y2 <= 0;
		//cntinu_cnt_old_y2 <= 0;
		//st_old_y2 <= AIS;
		
		ptr_vlue_old_y3 <= 0;
		allone_cnt_old_y3 <= 0;
		newp_inv_cnt_old_y3 <= 0;
		cntinu_cnt_old_y3 <= 0;
		st_old_y3 <= AIS;
		
		ptr_vlue_old_p <= 0;
		ptr_n_vlue_old_p <= 0;
		newp_inv_cnt_old_p <= 0;
		cntinu_cnt_old_p <= 0;
		st_old_p <= AIS;
		
		ptr_vlue_new_y1 <= 0;
		allone_cnt_new_y1 <= 0;
		newp_inv_cnt_new_y1 <= 0;
		continue_cnt_y1 <= 0;
		st_new_y1 <= AIS;
		end
	else
		begin
		//ptr_vlue_old_y2 <= ptr_vlue_old_y1;
		//allone_cnt_old_y2 <= allone_cnt_old_y1;
		//newp_inv_cnt_old_y2 <= newp_inv_cnt_old_y1;
		//cntinu_cnt_old_y2 <= cntinu_cnt_old_y1;
		//st_old_y2 <= st_old_y1;
		
		ptr_vlue_old_y3 <= ptr_vlue_old_y2;
		allone_cnt_old_y3 <= allone_cnt_old_y2;
		newp_inv_cnt_old_y3 <= newp_inv_cnt_old_y2;
		cntinu_cnt_old_y3 <= cntinu_cnt_old_y2;
		st_old_y3 <= st_old_y2;
		
		ptr_vlue_old_p <= ptr_vlue_old_y3;
		ptr_n_vlue_old_p <= ptr_n_vlue_old_y3;
		newp_inv_cnt_old_p <= newp_inv_cnt_old_y3;
		cntinu_cnt_old_p <= cntinu_cnt_old_y3;
		st_old_p <= st_old_y3;
		
		ptr_vlue_new_y1 <= ptr_vlue_new;
		allone_cnt_new_y1 <= allone_cnt_new;
		newp_inv_cnt_new_y1 <= newp_inv_cnt_new;
		continue_cnt_y1 <= continue_cnt;
		st_new_y1 <= st_new;
		end
end

wire	[11:0]		null_0;

//AU8_ITPRE_ST_RAM64x20 	U_ITPRE_ST_RAM64x20(
//	.clock			(rx_clk155m),
//	.wren			(h2_pos_y5),
//	.wraddress		({5'd0,hp_chan_y6}),
//	.data			({12'd0,ptr_vlue_new_y1,allone_cnt_new_y1,newp_inv_cnt_new_y1,continue_cnt_y1,st_new_y1}),

//	.rdaddress		({5'd0,hp_chan_y1}),
	//.q				({null_0,ptr_vlue_old_y1,allone_cnt_old_y1,newp_inv_cnt_old_y1,cntinu_cnt_old_y1,st_old_y1})
//	.q				({null_0,ptr_vlue_old_y2,allone_cnt_old_y2,newp_inv_cnt_old_y2,cntinu_cnt_old_y2,st_old_y2})
//	);


AU8_ITPRE_ST_RAM64x20          U_ITPRE_ST_RAM64x20(
   .clka                       ( rx_clk155m ),
   .wea                        ( h2_pos_y5 ),
   .addra                      ( {5'd0,hp_chan_y6} ),
   .dina                       ( {12'd0,ptr_vlue_new_y1,allone_cnt_new_y1,newp_inv_cnt_new_y1,continue_cnt_y1,st_new_y1} ),
   .clkb                       ( rx_clk155m ),
   .addrb                      ( {5'd0,hp_chan_y1} ),
   .doutb                      ( {null_0,ptr_vlue_old_y2,allone_cnt_old_y2,newp_inv_cnt_old_y2,cntinu_cnt_old_y2,st_old_y2} )
   );

always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		begin
		ptr_itpre_st1 <= 2'b00;
		ptr_itpre_st2 <= 2'b00;
		ptr_itpre_st3 <= 2'b00;
		ptr_itpre_st4 <= 2'b00;
		ptr_itpre_st5 <= 2'b00;
		ptr_itpre_st6 <= 2'b00;
		ptr_itpre_st7 <= 2'b00;
		ptr_itpre_st8 <= 2'b00;
		end
	else
		case(hp_chan_y3)
			3'd0:begin
				if(st_old_y2==LOP)
					ptr_itpre_st1 <= 2'b01;
				else if(st_old_y2==AIS)
					ptr_itpre_st1 <= 2'b10;
				else
					ptr_itpre_st1 <= 2'b00;
				end
			3'd1:begin
				if(st_old_y2==LOP)
					ptr_itpre_st2 <= 2'b01;
				else if(st_old_y2==AIS)
					ptr_itpre_st2 <= 2'b10;
				else
					ptr_itpre_st2 <= 2'b00;
				end
			3'd2:begin
				if(st_old_y2==LOP)
					ptr_itpre_st3 <= 2'b01;
				else if(st_old_y2==AIS)
					ptr_itpre_st3 <= 2'b10;
				else
					ptr_itpre_st3 <= 2'b00;
				end
			3'd3:begin
				if(st_old_y2==LOP)
					ptr_itpre_st4 <= 2'b01;
				else if(st_old_y2==AIS)
					ptr_itpre_st4 <= 2'b10;
				else
					ptr_itpre_st4 <= 2'b00;
				end
			3'd4:begin
				if(st_old_y2==LOP)
					ptr_itpre_st5 <= 2'b01;
				else if(st_old_y2==AIS)
					ptr_itpre_st5 <= 2'b10;
				else
					ptr_itpre_st5 <= 2'b00;
				end
			3'd5:begin
				if(st_old_y2==LOP)
					ptr_itpre_st6 <= 2'b01;
				else if(st_old_y2==AIS)
					ptr_itpre_st6 <= 2'b10;
				else
					ptr_itpre_st6 <= 2'b00;
				end
			3'd6:begin
				if(st_old_y2==LOP)
					ptr_itpre_st7 <= 2'b01;
				else if(st_old_y2==AIS)
					ptr_itpre_st7 <= 2'b10;
				else
					ptr_itpre_st7 <= 2'b00;
				end
			3'd7:begin
				if(st_old_y2==LOP)
					ptr_itpre_st8 <= 2'b01;
				else if(st_old_y2==AIS)
					ptr_itpre_st8 <= 2'b10;
				else
					ptr_itpre_st8 <= 2'b00;
				end
		endcase
end

//******************************************
always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		col0_en <= 0;
	else
		if(cnt3_col == 0)
			col0_en <= 1;
		else
			col0_en <= 0;
end

always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		begin
		hp_spe_y1 <= 1'b0;
		hp_spe_y2 <= 1'b0;
		h31h32h33_pos_y1 <= 1'b0;
		h31h32h33_pos_y2 <= 1'b0;
		h33_nn1n2_pos_y1 <= 1'b0;
		h33_nn1n2_pos_y2 <= 1'b0;
		col0_en_y1 <= 1'b0;
		col0_en_y2 <= 1'b0;
		col0_en_y3 <= 1'b0;
		col0_en_y4 <= 1'b0;
		col0_en_y5 <= 1'b0;
		spe_tmp_y1 <= 1'b0;
		spe_tmp_y2 <= 1'b0;
		spe_tmp_y3 <= 1'b0;
		end
	else
		begin
		hp_spe_y1 <= hp_spe;
		hp_spe_y2 <= hp_spe_y1;
		h31h32h33_pos_y1 <= h31h32h33_pos;
		h31h32h33_pos_y2 <= h31h32h33_pos_y1;
		h33_nn1n2_pos_y1 <= h33_nn1n2_pos;
		h33_nn1n2_pos_y2 <= h33_nn1n2_pos_y1;
		col0_en_y1 <= col0_en;
		col0_en_y2 <= col0_en_y1;
		col0_en_y3 <= col0_en_y2;
		col0_en_y4 <= col0_en_y3;
		col0_en_y5 <= col0_en_y4;
		spe_tmp_y1 <= spe_tmp;
		spe_tmp_y2 <= spe_tmp_y1;
		spe_tmp_y3 <= spe_tmp_y2;
		end
end
		
always @ (st_old_y2 or hp_spe_y2 or h31h32h33_pos_y2 or h33_nn1n2_pos_y2)
begin
	if(hp_spe_y2 == 1'b1)
		casex(st_old_y2)
		INC:begin
			if((h31h32h33_pos_y2 == 1'b1)||(h33_nn1n2_pos_y2 == 1'b1))
				spe_tmp <= 1'b0;
			else
				spe_tmp <= 1'b1;
			end
		DEC:spe_tmp <= 1'b1;
		default:begin
			if(h31h32h33_pos_y2 == 1'b1)
				spe_tmp <= 1'b0;
			else
				spe_tmp <= 1'b1;
		end
		endcase
	else
		spe_tmp <= 1'b0;
end

always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		j1_marker_old_y4 <= 0;
	else
		j1_marker_old_y4 <= j1_marker_old_y3;
end

always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		j1_marker_eq_MAX <= 0;
	else if(j1_marker_old_y3 >= PTR_MAX)
		j1_marker_eq_MAX <= 1;
	else
		j1_marker_eq_MAX <= 0;
end

always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		j1_marker <= 0;
	else if(h2_pos_y4 == 1'b1)
		j1_marker <= 0;
	else if((spe_tmp_y2==1'b1)&&(col0_en_y4==1'b1))
		if(j1_marker_eq_MAX == 1)
			j1_marker <= 0;
		else
			j1_marker <= j1_marker_old_y4 + 1;
end


wire	[5:0]	null_j1;	
//AU8_J1MARKER_RAM64x15	U_J1MARKER_RAM64x15(
//	.clock			(rx_clk155m),
//	.wren			(((spe_tmp_y3&col0_en_y5)|h2_pos_y5)),
//	.wraddress		({5'd0,hp_chan_y6}),
//	.data			({6'd0,j1_marker}),

//	.rdaddress		({5'd0,hp_chan_y2}),
//	.q				({null_j1,j1_marker_old_y3})
//	);



AU8_J1MARKER_RAM64x15          AU8_J1MARKER_RAM64x15(
   .clka                       ( rx_clk155m ),
   .wea                        ( ((spe_tmp_y3&col0_en_y5)|h2_pos_y5) ),
   .addra                      ( {5'd0,hp_chan_y6} ),
   .dina                       ( {6'd0,j1_marker} ),
   .clkb                       ( rx_clk155m ),
   .addrb                      ( {5'd0,hp_chan_y2} ),
   .doutb                      ( {null_j1,j1_marker_old_y3} )
   );


always @ (posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		fp_out <= 1'b0;
	else
		fp_out <= fp_to_ppfa_y4;
end
	
always @ (posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		j1_out <= 1'b0;
	else if((j1_marker_old_y3==ptr_vlue_old_y3)&&(col0_en_y3==1'b1)&&(spe_tmp_y1==1'b1))
		j1_out <= 1'b1;
	else
		j1_out <= 1'b0;
end

always @ (posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		begin
		spe_out <= 0;
		data_out <= 0;
		end
	else
		begin
		spe_out <= spe_tmp_y1;
		data_out <= data_in_y3;
		end
end

//*********************************
always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		begin
		waddr_pl_h_t1 <= 0;
		waddr_pl_h_t2 <= 0;
		waddr_pl_h_t3 <= 0;
		waddr_pl_h_t4 <= 0;
		waddr_pl_h_t5 <= 0;
		waddr_pl_h_t6 <= 0;
		waddr_pl_h_t7 <= 0;
		waddr_pl_h_t8 <= 0;
		end
	else if((spe_tmp==1'b1)&&(cnt3_col_y3==2'd0))
		case(hp_chan_y3)
			3'd0:waddr_pl_h_t1 <= waddr_pl_h_t1 + 1;
			3'd1:waddr_pl_h_t2 <= waddr_pl_h_t2 + 1;
			3'd2:waddr_pl_h_t3 <= waddr_pl_h_t3 + 1;
			3'd3:waddr_pl_h_t4 <= waddr_pl_h_t4 + 1;
			3'd4:waddr_pl_h_t5 <= waddr_pl_h_t5 + 1;
			3'd5:waddr_pl_h_t6 <= waddr_pl_h_t6 + 1;
			3'd6:waddr_pl_h_t7 <= waddr_pl_h_t7 + 1;
			3'd7:waddr_pl_h_t8 <= waddr_pl_h_t8 + 1;
		endcase
end


always @(posedge rx_clk155m or posedge reset)
begin
	if(reset == 1'b1)
		waddr_pl_h <= 5'd0;
	else
		case(hp_chan_y4)
			3'd0:waddr_pl_h <= waddr_pl_h_t1;
			3'd1:waddr_pl_h <= waddr_pl_h_t2;
			3'd2:waddr_pl_h <= waddr_pl_h_t3;
			3'd3:waddr_pl_h <= waddr_pl_h_t4;
			3'd4:waddr_pl_h <= waddr_pl_h_t5;
			3'd5:waddr_pl_h <= waddr_pl_h_t6;
			3'd6:waddr_pl_h <= waddr_pl_h_t7;
			3'd7:waddr_pl_h <= waddr_pl_h_t8;
		endcase
end

assign waddr_pl = {hp_chan_y5,waddr_pl_h,cnt3_col_y5};
assign wdata_pl[8:0] = {j1_out,data_out};
assign wen_pl = spe_out;



endmodule